1. Field of the Invention
This invention relates to bubble domain memory devices and, more particularly, to a serial shift register arrangement incorporating multiple loops and redundancy.
2. Description of the Prior Art
Presently, bubble domain memory devices having serial first-in first-out (FIFO) organization are best implemented by the simple serial shift register. In order to decrease the cost and improve the reliability of a memory storage system based on the serial shift register, it is necessary to increase the capacity of each memory chip by increasing the chip size. Unfortunately, the processing yield decreases with increasing chip size.
Organizations which incorporate redundancy are logical alternatives to the simple serial shift organization. However, the existing organizations have shortcomings which offset or decrease any potential increase in processing yield attributable to redundancy. For example, major/minor loop organizations, on-chip decoding organizations and bi-polar or quadrature organizations all introduce blanks in the data stream or require additional logic and on-chip logic modifications to eliminate the data blanks. Also, each of these organizations results in considerably increased complexity in processing, which translates into reduced processing yield. Obviously, such organizations can be very costly.
As may be appreciated, it is desirable to provide a serial FIFO organization which realizes the potential increased yield of redundancy without problems such as degradation of reliability or performance.